1. Field of the Invention
The present invention relates to the field of integrated circuits and more specifically to the fabrication of an NPN transistor.
2. Discussion of the Related Art
In patent application filed on even day herewith under attorney docket number S1022/7945 and incorporated herein by reference, a method for fabricating a bipolar transistor compatible with a BICMOS technology (that is, a technology enabling the simultaneous fabrication of bipolar transistors and of complementary MOS transistors) is described.
An example of NPN transistor obtained by using a BICMOS technology is shown in FIG. 12A of the above-mentioned patent application, which is reproduced in appended FIG. 1.
This NPN transistor is formed in an epitaxial layer 2 which is above a buried layer 3 formed in a P-type silicon substrate (not shown). The transistor is formed in a window made in a thick oxide layer 5. References 21 and 22 designate thin silicon oxide and silicon nitride layers which are used to protect other elements of the integrated circuit (such as CMOS transistors) during the fabrication of the bipolar transistor. Reference 23 designates a portion of a P-type doped polysilicon layer called base polysilicon since the base contact diffusion 32 is formed from this silicon layer. Polysilicon layer 23 is coated with an encapsulation silicon oxide layer 24. A central emitter-base opening is formed in layers 23 and 24 altogether. A thin silicon oxide layer 31 covers the sides of polysilicon layer 23 and the bottom of the opening. In this opening, an N-type high energy implant meant for forming a sub-collector region with a selected doping level is performed. The walls of the emitter-base opening are coated with a silicon nitride layer 44. Polysilicon lateral spacers 43 are formed on the sides of the opening. Before the forming of silicon nitride region 44 and of polysilicon spacers 43, an intrinsic base implant 33 is formed. After the spacers have been formed, a highly-doped N-type polysilicon layer 46 from which is formed emitter region 49 is deposited. Polysilicon layer 46 is coated with an encapsulation oxide layer 47. The general structure is coated with an insulating and planarizing layer 51 through which are formed emitter contact openings 55 joining polysilicon layer 46 and base contact openings 56 joining polysilicon layer 23. Further, a collector contact (not shown) is made via an N-type drive-in 30 towards buried layer 3.
This transistor has a circular symmetry, the emitter being centrally positioned and the base polysilicon being ring-shaped around this emitter.